#include "clib_cycle.h"
#include "clib_core.h"
#include <rte_lcore.h>
#include <rte_ethdev.h>
#include "clib_module.h"

/** TODO 初始花 **/
clib_cycle_t clib_cycle_conf;

i32_t clib_load_cycle(clib_core_conf_t* core)
{
    u16_t                port_id;
    clib_cycle_t        *gcycle;
    clib_lcore_cycle_t  *lcycle;
    clib_port_node_t    *port;
    i08_t                name[256];
    clib_config_t       *elem[1024];
    i32_t                elem_cnt;
    clib_config_t       *entry;

    i32_t  lcore_id  = rte_lcore_id();
    i32_t  socket_id = rte_lcore_to_socket_id(lcore_id);
    
    gcycle = &clib_cycle_conf;

    gcycle->lcore_cnt = clib_core_load.cpu_cnt;

    RTE_LCORE_FOREACH(lcore_id)
    {
        lcycle = &gcycle->lcore_cycle[lcore_id];
        lcycle->cycle     = gcycle;
        lcycle->lcore_id  = lcore_id;
        lcycle->socket_id = rte_lcore_to_socket_id(lcore_id);
    }
    
    gcycle->netif.port_cnt = rte_eth_dev_count_avail();

    if(!core->dpdk_dev != gcycle->netif.port_cnt)
    {
        clib_log_error("dpdk avail port not macth pci numbers\n");
        return rn_error;
    }

    RTE_ETH_FOREACH_DEV(port_id) {
        
        port = &gcycle->netif.port_conf[port_id];

        port->port_id = port_id;

        rte_eth_dev_get_name_by_port(port_id, port->pci);

        for(i32_t i = 0; i < gcycle->port_conf.port_cnt; i++) {
            if(!memcpy(core->dpdk_dev[i].pci, port->pci,strlen(port->pci))) {
                continue;
            }
            strcpy(port->pci,core->dpdk_dev[i].pci);
            strcpy(port->name,core->dpdk_dev[i].name);
            port->tx_queue = core->dpdk_dev[i].tx_queue;
            port->rx_queue = core->dpdk_dev[i].rx_queue;
        }
    }

    return rn_ok;
}